Infrared image sensors are widely used in a variety of applications. Many such sensors rely on pixels having a charge transimpedance amplifier (CTIA) pixel design.
Reset noise is a dominant noise source in CTIA-based pixels. One strategy for reducing such noise is the use of correlated double sampling (CDS), wherein the level of accumulated charge in the reset pixel is measured and this measurement is subtracted from the signal charge to remove the noise component. There can be significant overhead to implementing the CDS function downstream from the pixel, in that two successive reads are required, thus doubling the readout bandwidth requirements and impacting overall system power. It is therefore advantageous to be able to perform the CDS functionality within the pixel circuit. Accordingly, a pioneering in-pixel CDS function has been developed, as described in pending United States Patent Application Publication Number 20140016027 by Yang et al, entitled “In-Pixel CTIA Correlated Double Sampling with Snapshot Operation for IR Readout Integrated Circuits.”
A prior art CTIA-based IR readout integrated circuit (ROIC) Pixel with in-pixel CDS is shown in FIG. 1. The role of the CTIA is to maintain a fixed reverse-bias on the IR Photodetector (101), while integrating the photocurrent onto a feedback capacitor (105) thus converting it to a measureable voltage. The photodetector output line (102) inputs to the negative input of a single output differential amplifier (103). Before imaging can commence, the CTIA integration node voltage must be reset to a known value VRESET, by shorting the input and output of the CTIA amplifier together through reset switch 104. During this reset phase, the amplifier then drives the output (integration node) to the same voltage that is on the positive input of the buffer amplifier (106).
The correlated double sampling operation is achieved by using a clamp voltage 109. The clamp voltage is switched by a clamp switch 110 onto the output line. The timing of the operation is carried out by releasing the clamp switch 110 some period of time, e.g., 10-100 ns, after releasing the reset switch 104. This is based on the inventor's recognition that carrying out the reset causes a disturbance in the operational amplifier being used as the buffer. The system allows enough time for the resulting reset disturbance to settle transiently before the integration voltage is permitted to AC-couple to the other side of the correlated double sampling capacitor 108. Once the clamp voltage switch 110 is released, the reset level is stored across the correlated double sampling capacitor 108. Then, the correlated double sampling side of the capacitor 107 follows the normal integration of charge from the CTIA onto the integration node 112 and forms the resultant signal level for the pixel as the difference between the amount of charge at node 112 and the clamping value that was previously placed on node 113 and was stored across the capacitor 108. That signal forms the output signal which is input to the pixel readout circuit 111, for example comprising a source follower. This output signal is a linear function of the settled reset value and the integrated signal level, thus cancelling the reset noise. The reset noise is generated by the uncertainty in the total amount of charge (kTC noise) of the reset switch and is a function of the total input capacitance and feedback capacitance of the given CTIA circuit. For a high-gain CTIA, this reset noise can be hundreds or more electrons, input-referred. Therefore, removal of this noise source is critical for low-noise imaging operation.
The present invention builds upon the prior in-pixel CDS technologies by adding additional, optional functions to the pixel. Specifically, presented herein is an IR ROIC pixel design which can switch between low noise and high capacity modes.
An IR ROIC has a fixed well capacity of electrons that can be integrated per cycle, and also has an inherent noise signal. In a low light imaging context, it is advantageous to use a high gain amplifier, wherein a high signal to noise ratio insures that the low input signal is not swamped by noise. The sensitivity that is attained using a high gain amplifier is further enhanced if CDS operations are used as well. However, the use of a high gain amplifier means that the dynamic range of the pixel is reduced, and bright portions of a scene will saturate the well capacity of the sensor. In order to maximize pixel well capacity, the amplifier gain must be kept low, which is not ideal for dimly lit scenes where noise is an issue. The choice between maximizing sensitivity and maximizing capacity is not available in prior art IR sensor pixel designs, which are generally constrained to a single sensitivity and well capacity setting and are not optimized for both low and high light.
Advantageously, the present invention provides the art with a solution to this quandary. Disclosed herein is a novel pixel readout architecture which allows the pixel to be run in either a high sensitivity mode or a high capacity mode, as described below.